1. Field of the Invention
The present invention relates to semiconductor integrated circuits and those which are used as memory circuits, and more particularly, to semiconductor integrated circuits which reduce power consumption.
2. Description of the Prior Art
A memory circuit (usually, a flip-flop (hereinafter "FF")) is essential as a circuit which is used in a currently available semiconductor integrated circuit (LSI). FIGS. 11A and 11B are views showing an example of a structure of an FF which is used in a conventional semiconductor integrated circuit, as it is cut along a line A-A'. FIG. 11 is a general view showing the respective positions of FIGS. 11A and 11B. FIG. 11A shows a master side of the flip-flop circuit, while FIG. 11B shows a slave side of the flip-flop circuit. In FIGS. 11A and 11B, PTrX (X is an integer from 1 to 17) denotes a PMOS transistor, NTrX (X is an integer from 1 to 17) denotes an NMOS transistor, DX (X is an integer from 1 to 19) denotes a node, Q denotes an output, and *Q denotes an inverted output of the output Q. FIGS. 11A and 11B are contiguous to each other at the line A-A'. In FIGS. 11A and 11B, nodes V0, C0, D3, D5 and G0 are electrically connected to each other. The nodes V0 and V1 are electrically connected to power sources. The node C0 receives a clock signal (CLOCL). The nodes G0 and G1 are each grounded. The node D0 receives data (DATA).
A PMOS transistor is characterized in that it is turned on when the signal level at the gate is "L" level so that a current is conducted between a source electrode and a drain electrode from a high signal level side to a low signal level side. Further, a PMOS transistor is turned off when the signal level at the gate is "H" level, and a current is shut off between the source electrode and the drain electrode. Conversely, an NMOS transistor is characterized in that it is turned on when the signal level at the gate is "H" level so that a current is conducted between a source electrode and a drain electrode from a high signal level side to a low signal level side. Further, an NMOS transistor is turned off when the signal level at the gate is "L" level, and a current is shut off between the source electrode and the drain electrode. If a current is conducted and shut off between the source electrode and the drain electrode as described above depending on the signal level at the gate, a transistor is operating normally.
Next, an operation of the FF shown in FIGS. 11A and 11B will be described. It is assumed that data and the clock signal are both at "L" level. Since the clock signal is at "L" level, PTr2, PTr6, PTr10 and PTr12 are turned on, while NTr5, NTr7, NTr11 and NTr15 are turned off. Since the data are at "L" level, PTr1 and PTr7 are turned on, while NTr1 and NTr8 are turned off. As a result, the nodes D2, D7, D13 and D16 are at "H" level, while the nodes D6, D8, D12 and D17 are at "L" level. The node D1 is at "H" level.
Since PTr7 is already on, the circuit is conducted between the power source and the node D5. Hence, the node D5 is at "H" level. Since the node D1 is at "H" level, PTr3 is turned off and NTr2 is turned on.
Since the node D5 is at "H" level, PTr4 is turned off, while NTr3 and NTr4 are turned on. Further, PTr15 is turned off while NTr14 is turned on. Since NTr3 is turned on in addition to NTr2 which is already on, the circuit is conducted between the ground and the node D3. Hence, the node D3 is at "L" level.
As the node D3 is at "L" level, PTr5 is turned on, while NTr6 and NTr9 are turned off. Further, PTr9 is turned on and NTr10 is turned off.
Next, it is assumed that only the clock signal changes from "L" level to "H" level. As this happens, since the clock signal is at "H" level, PTr2, PTr6, PTr10 and PTr12 are turned off, and NTr5, NTr7, NTr11 and NTr15 are turned on.
Since NTr5 is turned on in addition to NTr4 which is already on, the node D3 which is already at "L" level remains at "L" level. As the node D3 stays at "L" level, the circuit is shut off between the node D5 and the ground, so that the node D5 is kept at "H" level.
Since NTr15 is turned on in addition to NTr14 which is already on, the node D14 is at "L" level. As a result, PTr8, PTr11 and PTr17 are turned on, and NTr12 and NTr17 are turned off. Hence, the output *Q is at "H" level.
Since NTr11 is turned on in addition to the node D13 which is already at "H" level, the node D11 is at "H" level. As the node D11 is at "H" level, PTr13, PTr14 and PTr16 are turned off, while NTr13 and NTr16 are turned on. Hence, the output Q is at "L" level.
Now, it is assumed that only the clock signal changes from "H" level to "L" level while the data remain at "L" level. As this happens, although the nodes D7 and D16 change to "H" level, the nodes D3, D5, D1 and D14 do not change but keep the current operation results ("H" level or "L" level at each node) described above. If the data remain unchanged as in this example, even though the clock signal changes, internal data do not change. The data can be held in this manner.
In a case where only the clock signal changes while the data remain at "H" level as well, although the signal levels at the nodes D3, D5, D11 and D14 are opposite to those described above, similar operation results are maintained.
In an actual operation of the circuit, however, the data do not necessarily maintain a constant signal level such as "H" level or "L" level. Although the signal level of the data appropriately changes while the circuit is in operation, the signal level of the data as it is currently in response to a change in the clock signal is maintained, as described above.
As described above, a function of temporarily maintaining a condition is realized by means of a change in the data and the clock signal, turning on and off of the transistors which are connected to the data and the clock signal, operations of the transistors which are turned on and off depending on "H" level and "L" level at the nodes which are connected to the transistors, etc. When such a function is realized, at gates which operate in synchronization to the clock signal within PTr2, PTr6, PTr10, PTr12, NTr5, NTr7, NTr11 and NTr15, capacities associated with the gates are charged or discharged. That is, a current is expended. Usually, a clock signal operates cyclically and most frequently in a synchronization type circuit, and therefore, power consumption which is equivalent to the eight transistors is very frequent.
Meanwhile, an integrated circuit device has an increasingly sophisticated performance and function in recent years. In a circuit which uses a number of memory circuit elements such as a microprocessor in accordance with this, power consumption is increasingly large. On the other hand, products such as recent type information equipment are desired to use less electric power while maintaining an advanced function.
In addition, a shorter research and development period is demanded. While an automatic design method such as a logic synthesizing system is widely adopted, with respect to supply of a clock signal to an FF which does not require an operation, a method adopted is to stop the clock signal by means of a control signal dandy a logic circuit. However, this method requires using a control signal and a circuit separately in order to realize this, and therefore, there are disadvantages such as an increased number of interconnectons, more difficulty in designing timing, and a longer period for designing. Thus, an element and a structure of an integrated circuit device which inherently expenses less power are urgently needed.